A semiconductor device formed of a semiconductor integrated circuit includes a pad serving as an external connection electrode. In the vicinity of the pad, an electrostatic discharge (ESD) protection circuit configured to protect an internal circuit of the semiconductor device against ESD is generally arranged. One kind of ESD protection circuits uses a multi-finger N-channel MOS transistor (hereinafter referred to as “NMOS transistor”) . In this case, the NMOS transistor has a gate and a source both connected to aground terminal, and a drain connected to a pad and an internal circuit (for example, see Patent Literature 1).